In producing semiconductors and more particularly FLASH EPROM devices, increasing the density of the device significantly enhances performance as well as cost effectiveness of the device. The typical way increasing the density has been accomplished is through the use of a so-called self aligned source (SAS) etching technique which provides for the proper formation of the FLASH cell. An example of this type of technique is disclosed in U.S. Pat. No. 5,120,671 entitled "PROCESS FOR SELF ALIGNING A SOURCE REGION WITH A FIELD OXIDE REGION AND A POLYSILICON GATE".
The above-identified patent discloses a method for forming a source region which is self-aligned with the poly word line as well as an apparatus formed thereby. In the patent, the end edges of the field oxide regions are vertically aligned with the poly word line with no bird's beak encroachment and corner rounding effect remaining in what will become the source region. The source region, formed between the ends of the field oxide regions of neighboring cells, is thus self-aligned with both the field oxide regions and the poly gate word lines. This self-alignment of the source region allows closer placement of poly word lines without any decrease in source width which thus requires less physical separation between (i.e., allows closer placement of) one memory cell to the next memory cell. Reduced cell size and greater overall device density is thus achieved.
In this example, the SAS etch is used after a stacked gate etch as a way to reduce overall cell size in a FLASH EPROM process. However, during the SAS etch, the stacked gate edge is exposed to the SAS etch, which has a significant negative impact on the tunnel oxide integrity. In addition, the building implants which consist mainly of the source diffusion implant are done after the SAS etch. Since the SAS etch has a tendency to etch away or gouge away silicon under the source region, the implant profiles might not be uniform at the source and may change the profile of the surface source that overlaps below the stacked gate. In that case, the erase integrity and erase distribution of the FLASH cell may be significantly degraded. As is well known, if the overlap area is too great, source coupling may be higher than and interfere with the erase operation. If the overlap area is too small, there may not be enough area for erasure. Typically due to the severity of SAS over-etch, erase is significantly impeded due to the lack of sufficient dose underneath the source overlap region.
Accordingly, what is needed is a system for ensuring that the overall cell size of semiconductor is reduced which doesn't have a negative impact on the tunnel oxide integrity of the device. In addition, the system should be one in which the implant profiles are uniform at the source overlap region, thereby ensuring cell integrity.
The present invention addresses these needs.